From 3c406378b20d19a86d076f7e991a4b3ba49a7f87 Mon Sep 17 00:00:00 2001
From: paulmart-n <hi@paulmartin.cloud>
Date: Mon, 29 Apr 2024 16:59:15 +0200
Subject: [PATCH] TRIS/DATA-Latch

---
 .../simulator/pic16f84/DataRegister.java      | 41 +++++++++++++-
 .../fabrik/simulator/pic16f84/IOPorts.java    | 54 +++++++++++++++++++
 2 files changed, 94 insertions(+), 1 deletion(-)
 create mode 100644 src/main/java/fabrik/simulator/pic16f84/IOPorts.java

diff --git a/src/main/java/fabrik/simulator/pic16f84/DataRegister.java b/src/main/java/fabrik/simulator/pic16f84/DataRegister.java
index 03663ba..4485594 100644
--- a/src/main/java/fabrik/simulator/pic16f84/DataRegister.java
+++ b/src/main/java/fabrik/simulator/pic16f84/DataRegister.java
@@ -7,6 +7,8 @@ public class DataRegister {
     private static final int PCL = 0x2;
     private static final int STATUS = 0x3;
     private static final int FSR = 0x4;
+    private static final int PORTA = 0x5;
+    private static final int PORTB = 0x6;
     private static final int PCLATH = 0xA;
     private static final int INTCON = 0xB;
 
@@ -21,6 +23,7 @@ public class DataRegister {
 
     private static final int [] dataRegister =  new int[0xFF];
     private static final int [] syncedRegisters = {INDF, PCL, STATUS, FSR, PCLATH, INTCON};
+    public static final int [] ioRegisters = {PORTA, PORTB, TRISA, TRISB};
 
     public static void initDataRegister() {
         dataRegister[PCL] = 0b0;
@@ -74,6 +77,10 @@ public class DataRegister {
 
     public static void setRegister(int fileAddress, int content){
         int address = determineIndirectAndChange (fileAddress);
+        if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
+            IOPorts.setRegister(address, content);
+            return;
+        }
         if (fileAddress == PCL || fileAddress == 0x80 + PCL){
             programCounter = content + (dataRegister[PCLATH] << 8);
         }
@@ -90,12 +97,16 @@ public class DataRegister {
         return (dataRegister[bank() + address] >> bit) & 1;
     }
 
-    private static int getDirectBit(int address, int bit){
+    public static int getDirectBit(int address, int bit){
         return (dataRegister[address] >> bit) & 1;
     }
 
     public static void clearBit(int fileAddress, int bit) {
         int address = determineIndirectAndChange (fileAddress);
+        if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
+            IOPorts.clearBit(address, bit);
+            return;
+        }
         if (!isSyncedRegister(address)) {
             if (getBit(address, bit) == 1) {
                 dataRegister[bank() + address] -= (int) Math.pow(2, bit);
@@ -111,6 +122,10 @@ public class DataRegister {
 
     public static void setBit(int fileAddress, int bit) {
         int address = determineIndirectAndChange (fileAddress);
+        if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
+            IOPorts.setBit(address, bit);
+            return;
+        }
         if (!isSyncedRegister(address)) {
             if (getBit(address, bit) == 0) {
                 dataRegister[bank() + address] += (int) Math.pow(2, bit);
@@ -231,4 +246,28 @@ public class DataRegister {
         return digitCarryFlag;
     }
 
+    public static void setDirectRegister(int fileAddress, int content) {
+        dataRegister[fileAddress] = content;
+    }
+
+
+    public static int getPCL() {
+        return PCL;
+    }
+    public static int getSTATUS() {
+        return STATUS;
+    }
+
+    public static int getPCLATH() {
+        return PCLATH;
+    }
+    public static int getINTCON() {
+        return INTCON;
+    }
+
+    public static int getDirectRegister(int address) {
+        return dataRegister[address];
+    }
 }
+
+
diff --git a/src/main/java/fabrik/simulator/pic16f84/IOPorts.java b/src/main/java/fabrik/simulator/pic16f84/IOPorts.java
new file mode 100644
index 0000000..9ca6f10
--- /dev/null
+++ b/src/main/java/fabrik/simulator/pic16f84/IOPorts.java
@@ -0,0 +1,54 @@
+package fabrik.simulator.pic16f84;
+
+public class IOPorts {
+    private static final int A = 0;
+    private static final int B = 1;
+    private static final int PORTA = 5;
+    private static final int PORTB = 6;
+    private static final int TRISA = 0x85;
+    private static final int TRISB = 0x86;
+
+    private static int [] trisLatch = new int[2];
+    private static int [] dataLatch = new int[2];
+
+    public static void setBit (int address, int bit){
+        if (address < 7) {
+            dataLatch[address - 5] |= (1 << bit);
+        }
+        else{
+            trisLatch[address - 0x85] |= (1 << bit);
+        }
+        refreshPorts();
+    }
+
+    public static void clearBit(int address, int bit) {
+        if (address < 7) {
+            if (DataRegister.getDirectBit(address, bit) == 1) {
+                int register = DataRegister.getDirectRegister(address);
+                dataLatch[address-A] = register - (int) Math.pow(2, bit);
+            }
+        }
+        else{
+            if (DataRegister.getDirectBit(address, bit) == 1) {
+                int register = DataRegister.getDirectRegister(address);
+                trisLatch[address-A] = register - (int) Math.pow(2, bit);
+            }
+        }
+        refreshPorts();
+    }
+
+    public static void setRegister(int address, int content) {
+        if (address < 7) {
+            dataLatch[address - 5] = content;
+        }
+        else{
+            trisLatch[address - 0x85] = content;
+        }
+        refreshPorts();
+    }
+
+    private static void refreshPorts() {
+        DataRegister.setDirectRegister(PORTA, (~((~dataLatch[A])&0xFF | trisLatch[A])) & 0x1F);
+        DataRegister.setDirectRegister(PORTB, (~((~dataLatch[B])&0xFF | trisLatch[B])) & 0xFF);
+    }
+}