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TRIS/DATA-Latch

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Paul Martin
2024-04-29 16:59:15 +02:00
parent b4f49dbb97
commit 3c406378b2
2 changed files with 94 additions and 1 deletions
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54
src/main/java/fabrik/simulator/pic16f84/IOPorts.java Normal file
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package fabrik.simulator.pic16f84;
public class IOPorts {
private static final int A = 0;
private static final int B = 1;
private static final int PORTA = 5;
private static final int PORTB = 6;
private static final int TRISA = 0x85;
private static final int TRISB = 0x86;
private static int [] trisLatch = new int[2];
private static int [] dataLatch = new int[2];
public static void setBit (int address, int bit){
if (address < 7) {
dataLatch[address - 5] |= (1 << bit);
}
else{
trisLatch[address - 0x85] |= (1 << bit);
}
refreshPorts();
}
public static void clearBit(int address, int bit) {
if (address < 7) {
if (DataRegister.getDirectBit(address, bit) == 1) {
int register = DataRegister.getDirectRegister(address);
dataLatch[address-A] = register - (int) Math.pow(2, bit);
}
}
else{
if (DataRegister.getDirectBit(address, bit) == 1) {
int register = DataRegister.getDirectRegister(address);
trisLatch[address-A] = register - (int) Math.pow(2, bit);
}
}
refreshPorts();
}
public static void setRegister(int address, int content) {
if (address < 7) {
dataLatch[address - 5] = content;
}
else{
trisLatch[address - 0x85] = content;
}
refreshPorts();
}
private static void refreshPorts() {
DataRegister.setDirectRegister(PORTA, (~((~dataLatch[A])&0xFF | trisLatch[A])) & 0x1F);
DataRegister.setDirectRegister(PORTB, (~((~dataLatch[B])&0xFF | trisLatch[B])) & 0xFF);
}
}