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PCLATCH + FSR

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This commit is contained in:
Paul Martin
2024-04-26 17:28:59 +02:00
parent 53767ac47f
commit b4f49dbb97
2 changed files with 36 additions and 13 deletions
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3
src/main/java/fabrik/simulator/pic16f84/Controller_FileSelect.java
View File

@ -41,6 +41,9 @@ public class Controller_FileSelect {
if (n != 0) {
Commands.decode(prog[DataRegister.getPC()]);
System.out.println("\nPC: " + DataRegister.getPC());
System.out.println("FSR: " + DataRegister.getFSR());
System.out.println("PCL: " + DataRegister.getRegister(0x2));
System.out.println("PCLATH: " + DataRegister.getRegister(0xA));
System.out.println("W: " + Commands.get_wRegister());
System.out.println("C: " + DataRegister.getCarryFlag());
System.out.println("DC: " + DataRegister.getDigitCarryFlag());

46
src/main/java/fabrik/simulator/pic16f84/DataRegister.java
View File

@ -3,6 +3,7 @@ package fabrik.simulator.pic16f84;
import java.util.Arrays;
public class DataRegister {
private static final int INDF = 0x0;
private static final int PCL = 0x2;
private static final int STATUS = 0x3;
private static final int FSR = 0x4;
@ -19,7 +20,7 @@ public class DataRegister {
private static final int [] dataRegister = new int[0xFF];
private static final int [] syncedRegisters = {PCL, STATUS, FSR, PCLATH, INTCON};
private static final int [] syncedRegisters = {INDF, PCL, STATUS, FSR, PCLATH, INTCON};
public static void initDataRegister() {
dataRegister[PCL] = 0b0;
@ -50,24 +51,42 @@ public class DataRegister {
return dataRegister;
}
private static int determineIndirectAndChange (int address){
if (address == INDF || address == 0x80 + INDF) {
return dataRegister[FSR];
}
else
return address;
}
public static int getFSR (){
return dataRegister[FSR];
}
private static int bank() {
return ((dataRegister[STATUS] >> RP0) & 1) * 0x80;
}
public static int getRegister(int fileAddress){
return dataRegister[bank() + fileAddress];
int address = determineIndirectAndChange (fileAddress);
return dataRegister[bank() + address];
}
public static void setRegister(int fileAddress, int content){
if (!isSyncedRegister(fileAddress))
dataRegister[bank() + fileAddress] = content;
int address = determineIndirectAndChange (fileAddress);
if (fileAddress == PCL || fileAddress == 0x80 + PCL){
programCounter = content + (dataRegister[PCLATH] << 8);
}
if (!isSyncedRegister(address))
dataRegister[bank() + address] = content;
else {
dataRegister[fileAddress] = content;
dataRegister[0x80 + fileAddress] = content;
dataRegister[address] = content;
dataRegister[0x80 + address] = content;
}
}
public static int getBit(int address, int bit) {
public static int getBit(int fileAddress, int bit) {
int address = determineIndirectAndChange (fileAddress);
return (dataRegister[bank() + address] >> bit) & 1;
}
@ -75,7 +94,8 @@ public class DataRegister {
return (dataRegister[address] >> bit) & 1;
}
public static void clearBit(int address, int bit) {
public static void clearBit(int fileAddress, int bit) {
int address = determineIndirectAndChange (fileAddress);
if (!isSyncedRegister(address)) {
if (getBit(address, bit) == 1) {
dataRegister[bank() + address] -= (int) Math.pow(2, bit);
@ -89,7 +109,8 @@ public class DataRegister {
}
}
public static void setBit(int address, int bit) {
public static void setBit(int fileAddress, int bit) {
int address = determineIndirectAndChange (fileAddress);
if (!isSyncedRegister(address)) {
if (getBit(address, bit) == 0) {
dataRegister[bank() + address] += (int) Math.pow(2, bit);
@ -106,12 +127,11 @@ public class DataRegister {
private static int programCounter = 0;
private static void writeToPCL(){
dataRegister[PCL] = programCounter;
dataRegister[0x82] = dataRegister[PCL];
dataRegister[PCL] = programCounter & 0xFF;
dataRegister[0x80 + PCL] = dataRegister[PCL];
}
public static void increasePC (){
programCounter = getRegister(PCL);
if (programCounter != 0x3FF) {
programCounter++;
}
@ -122,7 +142,7 @@ public class DataRegister {
}
public static void setPC (int value){
programCounter = value;
programCounter = value + ((getRegister(PCLATH) & 0b11000) << 8);
writeToPCL();
}