3 Commits

Author SHA1 Message Date
f932a141ce FIX Stack & IOPorts 2024-05-02 00:29:33 +02:00
3c406378b2 TRIS/DATA-Latch 2024-04-29 16:59:15 +02:00
b4f49dbb97 PCLATCH + FSR 2024-04-26 17:28:59 +02:00
4 changed files with 129 additions and 15 deletions

View File

@ -41,6 +41,9 @@ public class Controller_FileSelect {
if (n != 0) {
Commands.decode(prog[DataRegister.getPC()]);
System.out.println("\nPC: " + DataRegister.getPC());
System.out.println("FSR: " + DataRegister.getFSR());
System.out.println("PCL: " + DataRegister.getRegister(0x2));
System.out.println("PCLATH: " + DataRegister.getRegister(0xA));
System.out.println("W: " + Commands.get_wRegister());
System.out.println("C: " + DataRegister.getCarryFlag());
System.out.println("DC: " + DataRegister.getDigitCarryFlag());

View File

@ -3,9 +3,12 @@ package fabrik.simulator.pic16f84;
import java.util.Arrays;
public class DataRegister {
private static final int INDF = 0x0;
private static final int PCL = 0x2;
private static final int STATUS = 0x3;
private static final int FSR = 0x4;
private static final int PORTA = 0x5;
private static final int PORTB = 0x6;
private static final int PCLATH = 0xA;
private static final int INTCON = 0xB;
@ -19,7 +22,8 @@ public class DataRegister {
private static final int [] dataRegister = new int[0xFF];
private static final int [] syncedRegisters = {PCL, STATUS, FSR, PCLATH, INTCON};
private static final int [] syncedRegisters = {INDF, PCL, STATUS, FSR, PCLATH, INTCON};
public static final int [] ioRegisters = {PORTA, PORTB, TRISA, TRISB};
public static void initDataRegister() {
dataRegister[PCL] = 0b0;
@ -50,32 +54,59 @@ public class DataRegister {
return dataRegister;
}
private static int determineIndirectAndChange (int address){
if (address == INDF || address == 0x80 + INDF) {
return dataRegister[FSR];
}
else
return address;
}
public static int getFSR (){
return dataRegister[FSR];
}
private static int bank() {
return ((dataRegister[STATUS] >> RP0) & 1) * 0x80;
}
public static int getRegister(int fileAddress){
return dataRegister[bank() + fileAddress];
int address = determineIndirectAndChange (fileAddress);
return dataRegister[bank() + address];
}
public static void setRegister(int fileAddress, int content){
if (!isSyncedRegister(fileAddress))
dataRegister[bank() + fileAddress] = content;
int address = determineIndirectAndChange (fileAddress);
if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
IOPorts.setRegister(bank() + address, content);
return;
}
if (fileAddress == PCL || fileAddress == 0x80 + PCL){
programCounter = content + (dataRegister[PCLATH] << 8);
}
if (!isSyncedRegister(address))
dataRegister[bank() + address] = content;
else {
dataRegister[fileAddress] = content;
dataRegister[0x80 + fileAddress] = content;
dataRegister[address] = content;
dataRegister[0x80 + address] = content;
}
}
public static int getBit(int address, int bit) {
public static int getBit(int fileAddress, int bit) {
int address = determineIndirectAndChange (fileAddress);
return (dataRegister[bank() + address] >> bit) & 1;
}
private static int getDirectBit(int address, int bit){
public static int getDirectBit(int address, int bit){
return (dataRegister[address] >> bit) & 1;
}
public static void clearBit(int address, int bit) {
public static void clearBit(int fileAddress, int bit) {
int address = determineIndirectAndChange (fileAddress);
if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
IOPorts.clearBit(bank() + address, bit);
return;
}
if (!isSyncedRegister(address)) {
if (getBit(address, bit) == 1) {
dataRegister[bank() + address] -= (int) Math.pow(2, bit);
@ -89,7 +120,12 @@ public class DataRegister {
}
}
public static void setBit(int address, int bit) {
public static void setBit(int fileAddress, int bit) {
int address = determineIndirectAndChange (fileAddress);
if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
IOPorts.setBit(bank() + address, bit);
return;
}
if (!isSyncedRegister(address)) {
if (getBit(address, bit) == 0) {
dataRegister[bank() + address] += (int) Math.pow(2, bit);
@ -106,12 +142,11 @@ public class DataRegister {
private static int programCounter = 0;
private static void writeToPCL(){
dataRegister[PCL] = programCounter;
dataRegister[0x82] = dataRegister[PCL];
dataRegister[PCL] = programCounter & 0xFF;
dataRegister[0x80 + PCL] = dataRegister[PCL];
}
public static void increasePC (){
programCounter = getRegister(PCL);
if (programCounter != 0x3FF) {
programCounter++;
}
@ -122,7 +157,7 @@ public class DataRegister {
}
public static void setPC (int value){
programCounter = value;
programCounter = value + ((getRegister(PCLATH) & 0b11000) << 8);
writeToPCL();
}
@ -211,4 +246,28 @@ public class DataRegister {
return digitCarryFlag;
}
public static void setDirectRegister(int fileAddress, int content) {
dataRegister[fileAddress] = content;
}
public static int getPCL() {
return PCL;
}
public static int getSTATUS() {
return STATUS;
}
public static int getPCLATH() {
return PCLATH;
}
public static int getINTCON() {
return INTCON;
}
public static int getDirectRegister(int address) {
return dataRegister[address];
}
}

View File

@ -0,0 +1,52 @@
package fabrik.simulator.pic16f84;
public class IOPorts {
private static final int A = 0;
private static final int B = 1;
private static final int PORTA = 5;
private static final int PORTB = 6;
private static final int TRISA = 0x85;
private static final int TRISB = 0x86;
private static int [] trisLatch = new int[2];
private static int [] dataLatch = new int[2];
public static void setBit (int address, int bit){
if (address < 7) {
dataLatch[address - PORTA] |= (1 << bit);
}
else{
trisLatch[address - TRISA] |= (1 << bit);
}
refreshPorts();
}
public static void clearBit(int address, int bit) {
if (address < 7) {
if (((dataLatch[address-PORTA] >> bit)&1) == 1){
dataLatch[address-PORTA] -= (int) Math.pow(2, bit);
}
}
else{
if (DataRegister.getDirectBit(address, bit) == 1) {
trisLatch[address-TRISA] -= (int) Math.pow(2, bit);
}
}
refreshPorts();
}
public static void setRegister(int address, int content) {
if (address < 7) {
dataLatch[address - PORTA] = content;
}
else{
trisLatch[address - TRISA] = content;
}
refreshPorts();
}
private static void refreshPorts() {
System.out.println("PORTA: " + DataRegister.getDirectRegister(PORTA) + "; DATALATCHA: " + dataLatch[A] + "; TRISA: " + trisLatch[A]);
System.out.println("PORTB: " + DataRegister.getDirectRegister(PORTB) + "; DATALATCHB: " + dataLatch[B] + "; TRISB: " + trisLatch[B]);
}
}

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@ -17,7 +17,7 @@ public class ProgramStack {
}
public static void push(int value) {
if (returnStack.size() != 8) {
if ((returnStack.size() != 8 ) && (returnStack.size() <= stackIndex)){
returnStack.add(value);
incIndex();
}