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3 Commits
luca-zwisc
...
paul-zwisc
| Author | SHA1 | Date | |
|---|---|---|---|
| f932a141ce | |||
| 3c406378b2 | |||
| b4f49dbb97 |
@ -41,6 +41,9 @@ public class Controller_FileSelect {
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if (n != 0) {
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Commands.decode(prog[DataRegister.getPC()]);
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System.out.println("\nPC: " + DataRegister.getPC());
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System.out.println("FSR: " + DataRegister.getFSR());
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System.out.println("PCL: " + DataRegister.getRegister(0x2));
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System.out.println("PCLATH: " + DataRegister.getRegister(0xA));
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System.out.println("W: " + Commands.get_wRegister());
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System.out.println("C: " + DataRegister.getCarryFlag());
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System.out.println("DC: " + DataRegister.getDigitCarryFlag());
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@ -3,9 +3,12 @@ package fabrik.simulator.pic16f84;
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import java.util.Arrays;
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public class DataRegister {
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private static final int INDF = 0x0;
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private static final int PCL = 0x2;
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private static final int STATUS = 0x3;
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private static final int FSR = 0x4;
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private static final int PORTA = 0x5;
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private static final int PORTB = 0x6;
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private static final int PCLATH = 0xA;
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private static final int INTCON = 0xB;
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@ -19,7 +22,8 @@ public class DataRegister {
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private static final int [] dataRegister = new int[0xFF];
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private static final int [] syncedRegisters = {PCL, STATUS, FSR, PCLATH, INTCON};
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private static final int [] syncedRegisters = {INDF, PCL, STATUS, FSR, PCLATH, INTCON};
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public static final int [] ioRegisters = {PORTA, PORTB, TRISA, TRISB};
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public static void initDataRegister() {
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dataRegister[PCL] = 0b0;
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@ -50,32 +54,59 @@ public class DataRegister {
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return dataRegister;
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}
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private static int determineIndirectAndChange (int address){
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if (address == INDF || address == 0x80 + INDF) {
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return dataRegister[FSR];
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}
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else
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return address;
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}
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public static int getFSR (){
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return dataRegister[FSR];
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}
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private static int bank() {
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return ((dataRegister[STATUS] >> RP0) & 1) * 0x80;
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}
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public static int getRegister(int fileAddress){
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return dataRegister[bank() + fileAddress];
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int address = determineIndirectAndChange (fileAddress);
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return dataRegister[bank() + address];
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}
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public static void setRegister(int fileAddress, int content){
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if (!isSyncedRegister(fileAddress))
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dataRegister[bank() + fileAddress] = content;
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int address = determineIndirectAndChange (fileAddress);
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if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
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IOPorts.setRegister(bank() + address, content);
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return;
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}
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if (fileAddress == PCL || fileAddress == 0x80 + PCL){
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programCounter = content + (dataRegister[PCLATH] << 8);
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}
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if (!isSyncedRegister(address))
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dataRegister[bank() + address] = content;
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else {
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dataRegister[fileAddress] = content;
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dataRegister[0x80 + fileAddress] = content;
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dataRegister[address] = content;
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dataRegister[0x80 + address] = content;
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}
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}
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public static int getBit(int address, int bit) {
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public static int getBit(int fileAddress, int bit) {
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int address = determineIndirectAndChange (fileAddress);
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return (dataRegister[bank() + address] >> bit) & 1;
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}
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private static int getDirectBit(int address, int bit){
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public static int getDirectBit(int address, int bit){
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return (dataRegister[address] >> bit) & 1;
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}
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public static void clearBit(int address, int bit) {
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public static void clearBit(int fileAddress, int bit) {
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int address = determineIndirectAndChange (fileAddress);
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if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
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IOPorts.clearBit(bank() + address, bit);
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return;
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}
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if (!isSyncedRegister(address)) {
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if (getBit(address, bit) == 1) {
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dataRegister[bank() + address] -= (int) Math.pow(2, bit);
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@ -89,7 +120,12 @@ public class DataRegister {
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}
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}
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public static void setBit(int address, int bit) {
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public static void setBit(int fileAddress, int bit) {
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int address = determineIndirectAndChange (fileAddress);
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if (Arrays.stream(ioRegisters).anyMatch(i -> i == address)){
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IOPorts.setBit(bank() + address, bit);
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return;
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}
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if (!isSyncedRegister(address)) {
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if (getBit(address, bit) == 0) {
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dataRegister[bank() + address] += (int) Math.pow(2, bit);
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@ -106,12 +142,11 @@ public class DataRegister {
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private static int programCounter = 0;
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private static void writeToPCL(){
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dataRegister[PCL] = programCounter;
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dataRegister[0x82] = dataRegister[PCL];
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dataRegister[PCL] = programCounter & 0xFF;
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dataRegister[0x80 + PCL] = dataRegister[PCL];
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}
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public static void increasePC (){
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programCounter = getRegister(PCL);
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if (programCounter != 0x3FF) {
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programCounter++;
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}
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@ -122,7 +157,7 @@ public class DataRegister {
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}
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public static void setPC (int value){
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programCounter = value;
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programCounter = value + ((getRegister(PCLATH) & 0b11000) << 8);
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writeToPCL();
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}
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@ -211,4 +246,28 @@ public class DataRegister {
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return digitCarryFlag;
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}
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public static void setDirectRegister(int fileAddress, int content) {
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dataRegister[fileAddress] = content;
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}
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public static int getPCL() {
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return PCL;
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}
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public static int getSTATUS() {
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return STATUS;
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}
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public static int getPCLATH() {
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return PCLATH;
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}
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public static int getINTCON() {
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return INTCON;
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}
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public static int getDirectRegister(int address) {
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return dataRegister[address];
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}
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}
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52
src/main/java/fabrik/simulator/pic16f84/IOPorts.java
Normal file
52
src/main/java/fabrik/simulator/pic16f84/IOPorts.java
Normal file
@ -0,0 +1,52 @@
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package fabrik.simulator.pic16f84;
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public class IOPorts {
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private static final int A = 0;
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private static final int B = 1;
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private static final int PORTA = 5;
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private static final int PORTB = 6;
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private static final int TRISA = 0x85;
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private static final int TRISB = 0x86;
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private static int [] trisLatch = new int[2];
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private static int [] dataLatch = new int[2];
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public static void setBit (int address, int bit){
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if (address < 7) {
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dataLatch[address - PORTA] |= (1 << bit);
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}
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else{
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trisLatch[address - TRISA] |= (1 << bit);
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}
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refreshPorts();
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}
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public static void clearBit(int address, int bit) {
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if (address < 7) {
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if (((dataLatch[address-PORTA] >> bit)&1) == 1){
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dataLatch[address-PORTA] -= (int) Math.pow(2, bit);
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}
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}
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else{
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if (DataRegister.getDirectBit(address, bit) == 1) {
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trisLatch[address-TRISA] -= (int) Math.pow(2, bit);
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}
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}
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refreshPorts();
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}
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public static void setRegister(int address, int content) {
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if (address < 7) {
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dataLatch[address - PORTA] = content;
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}
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else{
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trisLatch[address - TRISA] = content;
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}
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refreshPorts();
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}
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private static void refreshPorts() {
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System.out.println("PORTA: " + DataRegister.getDirectRegister(PORTA) + "; DATALATCHA: " + dataLatch[A] + "; TRISA: " + trisLatch[A]);
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System.out.println("PORTB: " + DataRegister.getDirectRegister(PORTB) + "; DATALATCHB: " + dataLatch[B] + "; TRISB: " + trisLatch[B]);
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}
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}
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@ -17,7 +17,7 @@ public class ProgramStack {
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}
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public static void push(int value) {
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if (returnStack.size() != 8) {
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if ((returnStack.size() != 8 ) && (returnStack.size() <= stackIndex)){
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returnStack.add(value);
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incIndex();
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}
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